The introduction of high-k and metal gate materials in scaled CMOS technologies faces significant difficulties due to severe threshold voltage instability and performance degradation of the devices. These problems are related to the high amount of bulk defects and interface states in the high-k/metal gate stack, leading to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) issues.
In order to make high-k metal gates manufacturable, reliability must be improved. Fluorine is known to passivate high-k dielectric materials by reducing the number of interface and bulk defects. The bonds formed by fluorine in high-k dielectric materials are particularly strong and allow the passivation to be maintained despite the standard high temperature CMOS processing. Thus, fluorine passivation results in a robust defect passivation that allows better withstanding of the normal device operation conditions, leading to improved NBTI and PBTI behavior. A conventional method for fluorine incorporation uses a fluorine plasma implantation technique. However, this technique is difficult to control and often causes damage to the gate structure.
Accordingly, it is desirable to provide methods for fabricating integrated circuits with high-k dielectric material passivated by fluorine. In addition, it is desirable to provide methods for fabricating integrated circuits which avoid use of plasma implantation. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.